The present invention concerns an improved router used to connect core logic of a very large scale integrated (VLSI) circuit to a ring of I/O pads.
Once the logic for a VLSI integrated circuit has been developed, it is necessary to lay out the core logic for placement on a wafer die. Logic cells are arranged in mega-cell blocks. The mega-cell blocks are placed in a floor planning stage. Within the mega-cell blocks, standard logic cells are placed. This is followed by global routing of connectors between mega-cell blocks, and detail routing between standard logic cells within each mega-cell. Finally, pad ring routing is performed to interconnect the core logic to I/O pads of the circuit. The I/O pads will be bonded to package pins through bond wires.
When placing I/O pads on a wafer die, certain limitations are taken into account. For example, I/O pads must be placed on a wafer die so that bond wires will not cross. Additionally, it is generally required that bond wire length not exceed a specified maximum length. Also, the bond wire angle (the larger angle between the wire and the die edge) should be less than a specified maximum angle. Because of these bond limitations, it is generally desirable to place at least some I/O pads as close to the corners of a wafer die as possible.
Various methods are used to perform pad ring routing of I/O pads to core logic in a VLSI circuit. For example, a slicing structure with four channels may be used. In such a scheme, the pad ring is divided into four channels. The left and right channels are routed first, then the top and bottom channels. This method has several disadvantages. For example, big indentations in the top and bottom channels lead to inefficient routing. Further, because of the height of the top and bottom channels, gaps will result in the corners of the wafer die where it will be impossible to place I/O pads.
Alternately, moat routing may be used. See for example, Richard K. McGehee, A Practical Moat Router, 24th ACM/IEEE Design Automation Conference, 1987, pages 216-221. A moat is a channel bent into a ring, so that the horizontal tracks become concentric and the vertical columns become radial. A channel router can be modified to route the moat when the moat is unrolled. However, in the unrolled channel, trapezoids are connected at corner regions. If an I/O pad exists in one of these corner regions, a track for the I/O pad must be assigned so that it does not cause conflict with other nets padding through the corner area. A corner conflict can be resolved by moving the I/O pad a distance from the corner. This, however, can result in a gap between in the corners where no I/O pads are present. Further, the thickness of the moat is the same as the height or density of the channel. If the density is overestimated, the channel will be expanded and there will again be a large gap in the corners where there are no I/O pads. If the density is underestimated, the corner pads may abut preventing the channel from being compact. This can waste area of the wafer die.
A trapezoidal channel router may also be used to do pad ring routing. A floating edge between channels consists of a series of steps. Terminals between channels are placed on vertical edges of the steps. However, existing channel routers must be significantly modified to obtain such a trapezoidal channel router. Further, in the prior art use of trapezoid channel routers, there is still not significant placement of I/O pads in the corner of the wafer die.